Logic devices (e.g., a microprocessor providing digital data) generally operate within an output voltage range between about zero volts (0V) to about five volts (5V) or less to provide logic signals, and thus the logic device has a low voltage logic to enable higher switching speeds. The logic device receives a supply voltage that is generally derived from a battery voltage, and this supply voltage is typically substantially lower than the battery voltage. In some applications (e.g., automotive applications), the battery voltage is substantially greater than the output voltage range and the supply voltage for the logic device. For example, the battery voltage may be anywhere from about twelve volts (12V) to about twenty-eight volts (28V) or even greater.
Low voltage output buffers have been used to drive digital signals to logic devices with compliance between a low signal (e.g., about zero volts (0V)) and a high signal (e.g., about 2.5 to about five volts (5V)). In these buffers, the associated transistors that gate the supply voltage to the logic device may tolerate higher voltages than the logic device. In general, however, the greater the voltage, the slower the switching speeds of the transistors. When used in an automotive application or other application with more than one power supply, a short of the output buffer to the battery voltage may affect the reliability or disable the output buffer. For example, in an integrated circuit device, the port or pin corresponding to the output logic signal may be inadvertently connected (e.g., via improper soldering or incorrect PC board trace) to a port or pin designated to provide the battery voltage. Inadvertent coupling of the inputs to the logic device or the supply voltage inputs of the output buffer to these battery voltages would likely result in a short to the higher voltage and disable the output buffer.
Accordingly, a buffer circuit is desired that prevents damage to the buffer circuit from shorts to higher voltages while having sufficiently high switching speeds. More particularly, a buffer circuit for a low voltage logic device is desired that prevents damage to the buffer circuit from shorts to higher voltages. In addition, a method for buffering a signal to a low voltage logic device is desired that prevents damage from shorts to higher voltages. Furthermore, other desirable features and characteristics of the various embodiments will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.